EP910LC-35 vs EP910LC-35H Vergleich
Detaillierter Direktvergleich von EP910LC-35 von Altera und EP910LC-35H von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910LC-35 | EP910LC-35H |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,75 | $25,00 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Classic EPLD (EP910) |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM |
| Gehäuse | PLCC-44 (J-lead, LC suffix) | 40-pin Ceramic DIP (H suffix) |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range grade] |
| Pin-Anzahl | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | UV (quartz window on H package) |
| RoHS-Status | Not applicable (legacy product) | unknown |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 10 |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Ruhestrom | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Montageart | — | Through-hole (Ceramic DIP) |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |