EP910LC-40H vs EP910LC-40 Vergleich

Detaillierter Direktvergleich von EP910LC-40H von Altera und EP910LC-40 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910LC-40H EP910LC-40
Marke Altera Rochester Electronics
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $52,00
Family Classic EPLD (EP910) —
Macro Cells 24 —
Usable Gates 450 450
Logic Elements 24 macro cells / expandable to 48 via expander terms —
Propagation Delay (tPD) 40 ns max 40 ns
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
Supply Current (ICC) Low-power CMOS, typical ICC < 100 mA —
Technology CMOS, UV-erasable EPROM CMOS EPROM
Gehäuse 40-pin Ceramic DIP (CDIP-40), JEDEC standard PQCC-44 (Plastic Leaded Chip Carrier, J-lead)
Montageart Through-Hole (THT) —
Betriebstemperatur -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] —
Speed Grade -40 (40 ns tPD) —
Programming Method UV-erase + EPROM program, ~100 erase cycles Altera Logic Programmer (PLAD-J), 4-wire serial
I/O Pins [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] —
RoHS-Status [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] Not applicable (legacy)
Manufacturer — Rochester Electronics (Altera original)
Device Family — Altera Classic EPLD - EP910
Product Type — EPLD (Erasable Programmable Logic Device)
Macrocells — 24
Logic Array Blocks — 2 (12 macrocells each)
Maximum Toggle Frequency (fMAX) — 25 MHz
User I/O Pins — 36
Dedicated Inputs — 4
Operating Temperature (Commercial) — 0 C to +70 C
Lead-Free Status — Not applicable

Datenblätter & Ressourcen

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