EP910LI-30 vs EP910LI-20 Vergleich
Detaillierter Direktvergleich von EP910LI-30 von Rochester Electronics und EP910LI-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete
Spezifikationsvergleich
| Parameter | EP910LI-30 | EP910LI-20 |
|---|---|---|
| Marke | Rochester Electronics | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $49,50 | $19,95 |
| Family | Altera Classic EPLD EP910 | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Equivalent Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) | 5 V |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | — |
| Betriebstemperatur | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Gehäuse | 44-pin PQCC / PLCC-44 (J-lead) | 40-pin Ceramic DIP (Windowed) |
| Montageart | Surface Mount (socket recommended for UV erasure) | — |
| Dedicated Inputs | 10 | 16 |
| I/O Pins | 22 | 24 |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance not verified in scraped data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | — |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Technology | — | CMOS, UV-erasable |
| Package Type | — | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | — | Industrial (-40C to +85C) |
| Pin-Anzahl | — | 40 |
| Logic Family | — | EPLD (Erasable PLD) |
| Architecture | — | Sum-of-products macrocell |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |