EP910LI-35Y vs EP910LC-35 Vergleich
Detaillierter Direktvergleich von EP910LI-35Y von Intel und EP910LC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910LI-35Y | EP910LC-35 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,75 | $18,75 |
| Family | Altera Classic EPLD | Classic (EP910) |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | 24 |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | [DATA_NEEDED: maximum toggle frequency in MHz] | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Process Option | L (low-power CMOS) | — |
| Temperature Grade | Industrial (-40 °C to +85 °C) | — |
| Gehäuse | PLCC-44 (J-lead) | PLCC-44 (J-lead, LC suffix) |
| Montageart | Surface Mount | — |
| Lead Finish | Lead-free (Y suffix, RoHS-compliant) | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 36 | — |
| Technology | CMOS EPROM/UV-erasable | CMOS EPROM |
| RoHS-Status | Compliant (Y suffix) | Not applicable (legacy product) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Betriebstemperatur | — | 0C to +70C (commercial) |
| Pin-Anzahl | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |