EP910PC-25 vs EP910DC-15 Vergleich
Detaillierter Direktvergleich von EP910PC-25 von Altera und EP910DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-25 | EP910DC-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,92 | $10,75 |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | — |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V (typical) |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Gehäuse | PDIP-24 (Plastic DIP) | 24-pin ceramic DIP (DC) |
| Pin-Anzahl | 24 | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Altera Classic EPLD |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Montageart | — | Through-Hole |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| RoHS-Status | — | [DATA_NEEDED: not explicitly stated in verified data] |