EP910PC-25 vs EP910PC-0 Vergleich
Detaillierter Direktvergleich von EP910PC-25 von Altera und EP910PC-0 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-25 | EP910PC-0 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,92 | $8,70 |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | 900 gates |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| Technology | CMOS EPROM | — |
| Gehäuse | PDIP-24 (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| Pin-Anzahl | 24 | — |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EPLD |
| Logic Blocks | — | 6 (4 macrocells each) |
| I/O Pins | — | 24 |
| Speed Grade | — | -0 (slowest) |
| Versorgungsspannung | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable / OTP |
| Montageart | — | Through-Hole (DIP) |