EP910PI-12T vs EP910PI-25 Vergleich
Detaillierter Direktvergleich von EP910PI-12T von Altera und EP910PI-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PI-12T | EP910PI-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $10,95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | 5 V nominal |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| Gehäuse | 40-pin PDIP (Plastic DIP) | PDIP-40 (Plastic DIP) |
| Process Technology | CMOS | 5 V CMOS (EPROM-based) |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| RoHS-Status | Non-compliant (legacy PDIP package, contains lead) | Non-compliant (PDIP package) |
| Lebenszyklusstatus | NRND / EOL (mature legacy product) | — |
| Device | — | EP910 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Pin-Anzahl | — | 40 |
| Montageart | — | Through-Hole |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |