EP910PI-20 vs EP910PI-20T Vergleich

Detaillierter Direktvergleich von EP910PI-20 von Altera und EP910PI-20T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910PI-20 EP910PI-20T
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,75 $9,95
Device Family Altera Classic EPLD Family —
Macrocells 24 —
Propagation Delay (tPD) 20 ns —
Gehäuse PDIP-40 (PI suffix) PDIP-40 (PI)
Montageart Through-Hole Through-Hole (DIP)
Supply Voltage (VCC) 5 V (+/- 5%) —
Betriebstemperatur -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Technology CMOS EPROM (UV-erasable windowed variants available) CMOS EPROM (UV-erasable)
Configuration Method Non-volatile EPROM (no boot PROM required) —
Dedicated Inputs 12 —
Bidirectional I/O Pins 24 —
Maximum Counter Frequency 125 MHz —
Output Drive Current (IOL) 24 mA (TTL-compatible) —
Programmable Polarity Yes (XOR gate per macrocell) —
Macrocell Flip-Flop Yes (D-type, programmable) —
Power Dissipation [DATA_NEEDED: typical power dissipation in mW] —
Programming Interface JEDEC file via Altera programming hardware —
RoHS-Status unknown unknown
MIL-STD-883 Variant EP910DM/883B (separate part number) —
Family — Altera Classic EPLD
Device — EP910
Number of Macrocells — 24
Number of Usable Gates — [DATA_NEEDED: usable gate count]
Propagation Delay (tpd) — 20 ns
Maximum Toggle Frequency — 62.5 MHz
Number of Dedicated Inputs — 12
Number of I/O Pins — 20
Anzahl der Pins — 40
Programming — Standard EPROM programmer, JEDEC map
Lebenszyklusstatus — Not Recommended for New Designs (NRND)

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