EPC1441TC32 vs EPC1441LI20 Vergleich
Detaillierter Direktvergleich von EPC1441TC32 von Altera und EPC1441LI20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC1441TC32 | EPC1441LI20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $8,10 |
| Speichertyp | OTP Configuration PROM (flash-based) | OTP Configuration PROM (PROM) |
| Speichergröße | 440 Kbit (55000 byte) | — |
| Programmability | One-Time Programmable (OTP) | — |
| Versorgungsspannung | 3.3 V / 5.0 V | 3.3 V |
| Internal Oscillator | 16.7 MHz | — |
| In-System Programming | IEEE 1149.1 JTAG, 3.3 V / 5.0 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Configuration Modes | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous | — |
| Daisy Chain Support | Yes | — |
| Gehäuse | 32-TQFP (7 mm x 7 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Betriebstemperatur | Commercial (0C to +70C) | -40 C to +85 C (industrial) |
| Montageart | Surface Mount | — |
| Terminal Form | Gull Wing | — |
| Terminal Pitch | 0.8 mm | — |
| MSL-Level | 3 (168 hours) | [DATA_NEEDED: MSL rating] |
| RoHS-Status | [DATA_NEEDED: RoHS status - datasheet not yet verified] | [DATA_NEEDED: RoHS compliance status] |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Configuration Interface | — | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Pin Pitch | — | 1.27 mm |
| Programming Method | — | One-Time-Programmable via Altera programming hardware |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |