EPC144L20 vs EPC1441LI20 Vergleich
Detaillierter Direktvergleich von EPC144L20 von Altera und EPC1441LI20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC144L20 | EPC1441LI20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $8,10 |
| Speichertyp | OTP (One-Time Programmable) Configuration PROM | OTP Configuration PROM (PROM) |
| Memory Density | 440,800 bits | — |
| Speicherorganisation | 440,800 words × 1 bit (serial) | — |
| Schnittstelle | Altera serial configuration (4-pin: nCS, DCLK, DATA, nCONFIG) | — |
| Versorgungsspannung | 3.3 V | 3.3 V |
| Package Type | 20-pin LCC (Leadless Chip Carrier) | — |
| Betriebstemperatur | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Programming Method | OTP anti-fuse (single program cycle) | One-Time-Programmable via Altera programming hardware |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K, Mercury (legacy Altera) | — |
| Montageart | Surface Mount / Socket | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Configuration Clock | [DATA_NEEDED: max DCLK frequency] | — |
| Programming Voltage | [DATA_NEEDED: VPP] | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Configuration Interface | — | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Gehäuse | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Pitch | — | 1.27 mm |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |