EPC144LC-20 vs EPC144LC20 Vergleich
Detaillierter Direktvergleich von EPC144LC-20 von Altera und EPC144LC20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC144LC-20 | EPC144LC20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,15 | $7,10 |
| Speichertyp | OTP EPROM (One-Time Programmable) | — |
| Speichergröße | 440,800 bits (440 kb) | — |
| Configuration Interface | Altera serial daisy-chain | — |
| Access Time (Speed Grade) | 20 ns | — |
| Supply Voltage (VCC) | [DATA_NEEDED: VCC min/max] | 3.0 V to 5.5 V |
| Supply Voltage (VPP) | [DATA_NEEDED: VPP programming voltage] | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Package Type | 20-pin PLCC (J-lead) | — |
| Package Dimensions | 9 x 9 mm | — |
| Montageart | Surface Mount | Surface Mount |
| Compatible FPGA Families | FLEX 10K, FLEX 8000, ACEX 1K | — |
| Programming Method | Altera Logic Programmer / JTAG | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) |
| Process Technology | CMOS | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | 3 (168 hours) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status per Intel PCN] |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Daisy-Chain Support | Yes (multiple PROMs cascadable) | — |
| Manufacturer | Altera (now Intel FPGA) | — |
| Memory Capacity | — | 144 Kbit |
| Memory Organization | — | Serial (one-time programmable) |
| Schnittstellentyp | — | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Configuration Time (typical) | — | [DATA_NEEDED: configuration time at DCLK = 10 MHz] |
| Active Supply Current | — | [DATA_NEEDED: ICC active] |
| Standby Supply Current | — | [DATA_NEEDED: ICC standby] |
| Gehäuse | — | 20-pin LCC (Leadless Chip Carrier, JLCC-20) |
| Pin-Anzahl | — | 20 |
| Supported FPGA Families | — | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K |
| Halogenfrei | — | [DATA_NEEDED] |
| JTAG Compliance | — | IEEE Std 1149.1 |