EPC144LC20 vs EPC1LC20U Vergleich
Detaillierter Direktvergleich von EPC144LC20 von Intel und EPC1LC20U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPC144LC20 | EPC1LC20U |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $9,75 |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Schnittstellentyp | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | Altera APU / third-party JTAG programmer |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | — |
| Betriebstemperatur | -40C to +85C (industrial) | [DATA_NEEDED: industrial/commercial grade range] |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Gehäuse | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-pin PLCC (9x9 mm) |
| Pin-Anzahl | 20 | — |
| Montageart | Surface Mount | Surface Mount |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| MSL-Level | 3 (168 hours) | [DATA_NEEDED] |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status per Intel PCN] | Compliant (Pb-free finish, "U" suffix) |
| Lead-Free | Yes | — |
| Halogenfrei | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Speichertyp | — | OTP (One-Time-Programmable) Configuration PROM |
| Memory Density | — | 1 Mbit |
| Configuration Interface | — | Altera Serial Configuration (4-wire) |
| Maximum DCLK Frequency | — | 8 MHz |
| Operating Voltage (VCC) | — | 3.3 V typical [DATA_NEEDED: full range] |
| Configuration Time | — | [DATA_NEEDED: depends on bitstream length and DCLK] |
| Cascading Support | — | Yes (multi-PROM daisy-chain for larger bitstreams) |
| Lead-Free (Pb-free) Finish | — | Yes ("U" suffix) |
| Compatibility | — | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) |