EPC144PC8 vs EPC144PI8 Vergleich
Detaillierter Direktvergleich von EPC144PC8 von Intel und EPC144PI8 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC144PC8 | EPC144PI8 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,10 | $7,25 |
| Manufacturer | Altera (now Intel) | — |
| Part Type | Serial Configuration PROM / Configuration Device | — |
| Internal Manufacturer Number | 433800612 | — |
| Memory Technology | EPROM (one-time programmable) | — |
| Gehäuse / Bauform | DIP-8 (PDIP-8, through-hole) | — |
| Versorgungsspannung | 4.75 V to 5.25 V | — |
| Betriebstemperatur | 0 °C to +70 °C | -40C to +85C (industrial, 'I' suffix) |
| Schnittstelle | Altera serial configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | 4-wire serial (DCLK, DATA, nCS, nINIT_STATUS) |
| Compatible FPGA Series | Altera FLEX 8000, FLEX 10K, APEX 20K, EPF10K family | — |
| Programming Method | ByteBlaster / BitBlaster via Quartus or MAX+PLUS II | — |
| Configuration Mode | Passive Serial (PS) | — |
| Endurance | 100k write/erase cycles typical (EPROM) | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Montageart | Through-Hole (THT) | Through-hole (THT) |
| Memory Density | — | 144 Kbit (144,096 bits) |
| Speichertyp | — | OTP Serial Configuration EPROM (UV-erasable package option available) |
| Configuration Clock (max) | — | [DATA_NEEDED: DCLK maximum frequency] |
| Supply Voltage VCC | — | [DATA_NEEDED: VCC operating range] |
| Gehäuse | — | PDIP-8 (300 mil) |
| Pin-Anzahl | — | 8 |
| Process Technology | — | CMOS EPROM (1.8 V core option per suffix '8') |
| Programmability | — | One-Time Programmable (OTP) per bitstream; UV-erasable window package variant also exists |
| Target FPGA Compatibility | — | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX 20K (legacy) |
| MSL-Level | — | Not applicable (through-hole) |
| nINIT_STATUS Output | — | Open-drain, active-low (per datasheet family convention) |
| Power-On Reset | — | Internal automatic (per datasheet family convention) |