EPC16QC100SS vs EPC16QC-100T Vergleich

Detaillierter Direktvergleich von EPC16QC100SS von Intel und EPC16QC-100T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EPC16QC100SS EPC16QC100SS - 16Mb Config PROM for FPGAs, PQFP-100 | Intel

EPC16QC100SS - 16Mb Config PROM for FPGAs, PQFP-100 | Intel

EPC16QC100SS ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EPC16QC100SS EPC16QC-100T
Marke Intel Altera
Kategorie Memory ICs Memory ICs
Lebenszyklusstatus Letzte Kaufgelegenheit Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $13,20 $14,50
Speichertyp In-System Programmable Configuration PROM Flash Configuration PROM (in-system programmable)
Speichergröße 16 Mb (16,777,216 bits) —
Configuration Interface Passive Serial / Passive Parallel Synchronous / Passive Parallel Asynchronous —
Operating Modes FPGA configuration storage, ISP via IEEE 1532 —
Supply Voltage (VCC) 3.3 V (SS suffix variant) —
I/O Logic Level 3.3V or 2.5V selectable via VCCSEL —
Betriebstemperatur 0C to +70C (Commercial) [DATA_NEEDED: Operating temperature range]
Gehäuse 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
Montageart Surface Mount Surface Mount
Compatible FPGAs Stratix, Stratix II, Cyclone, Cyclone II, APEX 20K, other Altera FPGAs requiring >8 Mbit configuration —
Programmability In-system programmable (IEEE 1532) —
MSL-Level [DATA_NEEDED: MSL level] [DATA_NEEDED: Moisture sensitivity level]
RoHS-Status [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] unknown
Manufacturer Intel (formerly Altera) —
Memory Density — 16 Mbit (2 Mbyte)
Supported FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
Versorgungsspannung — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]

Datenblätter & Ressourcen

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