EPC16QI100T vs EPC16QI100TBAC Vergleich
Detaillierter Direktvergleich von EPC16QI100T von Altera und EPC16QI100TBAC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16QI100T | EPC16QI100TBAC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $15,95 |
| Product Type | Enhanced Configuration PROM (Flash) | — |
| Speichergröße | 16 Mbit | — |
| Versorgungsspannung | 3.3 V | 3.3 V |
| Configuration Data Width | Serial or 8-bit parallel (FPGA mode dependent) | — |
| Programmable Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Compression Support | Yes (Altera FPGA-side decompression) | — |
| Page-Mode Configuration | Yes (multi-device daisy chain) | — |
| Supported FPGAs | Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K | — |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Gehäuse | 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm | 100-pin PQFP (20 x 14 mm) |
| Montageart | Surface Mount | Surface Mount (PQFP) |
| Shipping Media | Tape and Reel (suffix T) | — |
| Configuration Controller | Built-in (nCONFIG, nSTATUS, CONF_DONE handshake) | Integrated |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | 3 (168 hours) |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Speichertyp | — | Flash (Enhanced Configuration Device) |
| Configuration Modes | — | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) |
| Maximum Configuration Clock | — | 40 MHz |
| Number of Configuration Pages | — | Up to 8 (selectable via PGM[2..0]) |
| In-System Programmable | — | Yes (via JTAG / IEEE 1149.1) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan and programming) |
| Supported FPGA Families | — | Altera Stratix, Cyclone, Arria series |
| Data Compression | — | Supported (15-30% density gain depending on target FPGA) |
| Lead-Free / RoHS | — | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] |
| Dynamic Reconfiguration | — | Yes (page mode via PGM[2..0] pins) |
| Programming Interface | — | JTAG / 4-wire passive serial |