EPC16SI16N vs EPC16QC100N Vergleich
Detaillierter Direktvergleich von EPC16SI16N von Intel und EPC16QC100N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPC16SI16N | EPC16QC100N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,35 | $24,10 |
| Speichertyp | Non-volatile flash (enhanced configuration device) | — |
| Speichergröße | 16 Mb (16,777,216 bits) | 16 Mbit (16,777,216 bits) |
| Schnittstelle | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) | — |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Maximum Operating Frequency | 40 MHz (fast configuration mode) | — |
| Betriebsversorgungsspannung | 3.3 V (typ) | — |
| Betriebstemperatur | -40 C to +85 C (industrial, 'SI' suffix) | 0 C to 70 C |
| Gehäuse | 16-pin SOIC (300 mil, 'SI' suffix) | 100-pin PQFP (20 x 14 mm) |
| Montageart | Surface Mount | Surface Mount |
| Lead-Free / Finish | Lead-free (matte tin), 'N' suffix | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | Compliant | — |
| In-System Programmability | Yes (via JTAG, multiple reprogramming cycles) | — |
| Compatible FPGA Series | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III | — |
| Configuration Daisy-Chaining | Supported (multiple devices / multiple FPGAs) | — |
| On-Chip Charge Pump | Integrated (no external VPP required) | — |
| Programmable Type | — | In System Programmable |
| Configuration Clock Frequency | — | 33 MHz max |
| On-Chip Decompression | — | Yes (supports compressed bitstreams) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Access Time | — | 90 ns typical |
| Flash Read Bandwidth | — | 160 Mbps (16-bit DQ at 10 MHz) |
| Configuration Interface | — | FPP / PS / AS via dedicated FPGA pins |
| JTAG (IEEE 1149.1) ISP | — | Supported |
| Lead Free | — | Yes (per datasheet) |
| Packaging | — | Tray |
| Supported FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |