EPC16UC88 vs EPC16UC8B Vergleich
Detaillierter Direktvergleich von EPC16UC88 von Altera und EPC16UC8B von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC16UC88 | EPC16UC8B |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | Unknown | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $7,10 |
| Device Type | In-system programmable configuration PROM for FPGAs | — |
| Configuration Memory Capacity | 16 Mb | — |
| Versorgungsspannung | 3.3 V core and I/O | — |
| Gehäuse | 88-UBGA (11x8) | 8-pin QFP (UC8B suffix) |
| Package Family | UBGA | — |
| In-System Programmability | IEEE Std. 1532 compatible | — |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | — |
| JTAG Boundary Scan | Supported | — |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | — |
| Configuration Architecture | Configuration controller and flash memory | — |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | — |
| Data Output | Configuration data output controlled by OE and nCS | — |
| Output Control | OE and nCS control tri-state buffer and address counter | — |
| Montageart | Surface mount | Surface Mount |
| Package Dimensions | 11 mm x 8 mm | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature] | [DATA_NEEDED: Operating temperature range] |
| Output Current | [DATA_NEEDED: output current] | — |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Product Type | — | Enhanced Configuration Device |
| Manufacturer | — | Intel (formerly Altera) |
| Configuration Memory Density | — | 16 Mb |
| FPGA Family Supported | — | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX) |
| Configuration Modes | — | Passive Serial (PS), Passive Parallel Asynchronous (PPA), Passive Parallel Synchronous (PPS), Fast Passive Parallel (FPP) |
| Core Supply Voltage (VCC) | — | 3.3 V |
| I/O Supply Voltage (VIO) | — | 1.8 V / 2.5 V / 3.3 V |
| Programmability | — | In-system programmable via IEEE 1532 / JTAG |
| Configuration Pages | — | 16 pages x 1 Mb each |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: Lead-free status] |
| Handshake Pins | — | nSTATUS, CONF_DONE, nCONFIG, OE |
| Family | — | EPC16 (Enhanced Configuration) |