EPC16UC88T vs EPC16UC88N Vergleich
Detaillierter Direktvergleich von EPC16UC88T von Altera und EPC16UC88N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC16UC88T | EPC16UC88N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | EEPROM | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $9,75 |
| Speichertyp | Non-volatile Flash configuration PROM (in-system programmable) | — |
| Memory Density | 16 Mbit (2,097,152 x 8 bits) | — |
| Configuration Interface | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF_DONE) | — |
| Maximum DCLK Frequency | 33 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| Betriebstemperaturbereich | -40 C to +85 C (industrial) | — |
| Gehäuse | 88-ball UBGA, 11 mm x 8 mm | — |
| In-System Programming | IEEE Std 1149.1 (JTAG) | — |
| Cascade Support | Yes (for higher density multi-PROM chains) | — |
| MSEL Compatibility | FPP / PS configuration modes (3.3 V legacy) | — |
| Compatible FPGA Families | Cyclone, Cyclone II, Stratix, Stratix II, Stratix III, Stratix IV, Arria GX | — |
| Family Density Step | Largest member of EPC4 / EPC8 / EPC16 family | — |
| RoHS-Status | [DATA_NEEDED: RoHS] | — |
| MSL-Level | [DATA_NEEDED: MSL] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Open-Drain nINIT_CONF_DONE | Yes | — |
| Speichergröße | — | 16 Mbit (16,777,216 bits) |
| Programmable Type | — | In System Programmable |
| Supply Voltage (Vcc) | — | 3.0 V to 3.6 V |
| Configuration Modes | — | Passive Serial (PS), Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), JTAG |
| On-Chip Decompression | — | Yes (Altera proprietary) |
| Gehäuse / Bauform | — | 88-UBGA (11x8 mm) / 88-LFBGA |
| Pin-Anzahl | — | 88 |
| Betriebstemperatur | — | 0 °C to +70 °C |
| Bus-Hold on Data Lines | — | Yes |
| Standby Mode | — | Yes (reduced power consumption) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| Programming Interface | — | JTAG (in-system) / Serial (in-system) |
| On-Chip Oscillator | — | Yes (internal configuration clock) |
| Lead-Free / RoHS | — | Lead-Free (per datasheet) |
| Montageart | — | Surface Mount |
| Packaging | — | Tray |