EPC16UC8B vs EPC16UC80 Vergleich
Detaillierter Direktvergleich von EPC16UC8B von Intel und EPC16UC80 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC16UC80 - 16Mb Enhanced Config Device, 80-pin UBGA | Altera
EPC16UC80 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16UC8B | EPC16UC80 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $11,75 |
| Product Type | Enhanced Configuration Device | — |
| Manufacturer | Intel (formerly Altera) | — |
| Configuration Memory Density | 16 Mb | — |
| FPGA Family Supported | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX) | — |
| Configuration Modes | Passive Serial (PS), Passive Parallel Asynchronous (PPA), Passive Parallel Synchronous (PPS), Fast Passive Parallel (FPP) | FPP, PS, JTAG |
| Core Supply Voltage (VCC) | 3.3 V | — |
| I/O Supply Voltage (VIO) | 1.8 V / 2.5 V / 3.3 V | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Configuration Pages | 16 pages x 1 Mb each | — |
| Gehäuse | 8-pin QFP (UC8B suffix) | 80-ball UBGA (Ultra FineLine BGA), 11x8 mm |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: Operating temperature range] | -40 C to +85 C (industrial) |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: Lead-free status] | — |
| Handshake Pins | nSTATUS, CONF_DONE, nCONFIG, OE | — |
| Family | EPC16 (Enhanced Configuration) | — |
| Memory Density | — | 16 Mbit |
| Device Family | — | EPC4 / EPC8 / EPC16 Enhanced Configuration Device |
| Configuration Memory Sections | — | 8 (multi-boot capable) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (typical 3.3 V) |
| Configuration Clock (DCLK) | — | Up to 33 MHz (FPP mode) |
| Schnittstelle | — | Parallel data + DCLK + nSTATUS + nCONFIG + CONFIG_DONE |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Endurance | — | 100,000 erase/program cycles (per datasheet) |
| Supported Target FPGAs | — | Stratix/II/III/GX, Cyclone/II/III, APEX 20K/II/IIE, Mercury |
| Lead-Free / RoHS | — | Compliant per Altera product page |
| Multi-Device Daisy-Chain | — | Yes |