EPC16UI88 vs EPC16UIC88 Vergleich
Detaillierter Direktvergleich von EPC16UI88 von Altera und EPC16UIC88 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC16UIC88 - 16Mb Enhanced Configuration Device | Altera/Intel
EPC16UIC88 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16UI88 | EPC16UIC88 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,21 | $10,20 |
| Memory Density | 16 Mb (2 MB) | — |
| Configuration Interface | Altera Passive Serial / Passive Parallel (Sync & Async) / JTAG | Parallel CMOS, FPP mode for legacy Altera FPGAs |
| Core Supply Voltage | 3.3 V | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Maximum Configuration Clock | 100 MHz | — |
| Cascading Support | Multi-device configuration chains | — |
| Supported FPGA Families | Altera Cyclone II/III/IV, Stratix II/III, APEX II | — |
| Gehäuse | 88-ball UBGA (Ultra FineLine BGA), 11x8 mm | UBGA-88 (Ultra FineLine BGA), 11 x 8 mm |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Standby Current | [DATA_NEEDED: standby current] | — |
| Active Configuration Current | [DATA_NEEDED: active configuration current] | — |
| Programming Cycles | [DATA_NEEDED: programming endurance cycles] | — |
| RoHS-Status | Compliant | [DATA_NEEDED: explicit RoHS status] |
| Configuration Time | [DATA_NEEDED: configuration time for typical 16 Mb bitstream] | — |
| Speichergröße | — | 16 Mb (1M x 16) |
| Speichertyp | — | Enhanced Configuration Device (flash-based, non-volatile) |
| Supply Voltage (VCC) | — | 3.3 V |
| In-System Programmability | — | Yes, JTAG IEEE Std 1149.1 |
| Program/Erase Cycles | — | [DATA_NEEDED: endurance spec] |
| Data Retention | — | 20 years minimum |
| Multi-Device Cascading | — | Yes, supports 2-device daisy-chain for 32 Mb |
| Configuration Handshake Pins | — | nCONFIG, nSTATUS, CONF_DONE |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Lead-Free Reflow | — | Yes, peak reflow 260C per JEDEC J-STD-020 |
| Process Technology | — | CMOS, 3.3 V core |