EPC1PC8CCD vs EPC1PC8CC Vergleich
Detaillierter Direktvergleich von EPC1PC8CCD von Intel und EPC1PC8CC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC1PC8CCD - 1Mb OTP Config PROM, 8-PDIP | Intel / Altera
EPC1PC8CCD ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC1PC8CCD | EPC1PC8CC |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $9,95 |
| Speichertyp | OTP Configuration PROM | EPROM (OTP, UV-erasable window optional) |
| Speichergröße | 1 Mbit (1,048,576 bits) | 1 Mbit (1,048,576 bits) |
| Schnittstelle | Serial (Altera EPC1 configuration interface) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| Programming Technology | Anti-fuse OTP (one-time programmable) | — |
| Cascading Support | Yes (daisy-chain, up to 8 devices) | — |
| Package Type | 8-PDIP (Plastic DIP, through-hole) | — |
| Pin-Anzahl | 8 | 8 |
| Betriebstemperaturbereich | 0 C to +70 C (Commercial) | [DATA_NEEDED: full industrial range from datasheet] |
| Lead Finish | NiPdAu (lead-free) | — |
| Configuration Clock | Internal oscillator (DATA clock to FPGA) | — |
| Compatible FPGA Families | Altera FLEX 6000/8000/10K, APEX 20K, ACEX 1K | ACEX 1K, APEX 20K, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, FLEX 8000, MAX 7000B/AE/S, MAX 9000, Mercury, Stratix, Stratix II, Arria |
| RoHS-Status | Compliant (lead-free "CCD" suffix) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | 1 (unlimited floor life) |
| Replacement Status | Last-time-buy; replaced by EPCS/EPCQ serial configuration devices | — |
| Funktion | — | FPGA Configuration PROM |
| Configuration Interface | — | Altera Passive Serial (PS), 4-wire (nSTATUS, nCONFIG, DCLK, DATA0) |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (typical 3.3 V) |
| Maximum DCLK Frequency | — | 17.6 MHz (17.6 Mb/s effective bitstream rate) |
| Gehäuse | — | PDIP-8 (Plastic DIP, 8-pin, 0.1" pitch) |
| Montageart | — | Through-Hole (DIP socketable) |
| Cascade Support | — | Not supported in DIP-8 package (nCASC pin not exposed) |
| Programming Interface | — | JTAG via Altera Quartus / Quartus Prime ByteBlaster |
| Error Detection | — | Built-in CRC during configuration transfer |
| Lead-Free / RoHS | — | Not lead-free (legacy Altera/Intel PC8 suffix is Sn-Pb finish); RoHS non-compliant variant |