EPC1PC8CEC vs EPC1PC8CC Vergleich
Detaillierter Direktvergleich von EPC1PC8CEC von Intel und EPC1PC8CC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC1PC8CEC | EPC1PC8CC |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,85 | $9,95 |
| Speichertyp | OTP Configuration PROM (non-volatile) | EPROM (OTP, UV-erasable window optional) |
| Speichergröße | 1 Mbit (1,046,496 bits) | 1 Mbit (1,048,576 bits) |
| Speicherorganisation | 1,046,496 x 1 bit (serial) | — |
| Configuration Interface | Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | Altera Passive Serial (PS), 4-wire (nSTATUS, nCONFIG, DCLK, DATA0) |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3 V typical) | 3.0 V to 3.6 V (typical 3.3 V) |
| Programming Method | Factory OTP (one-time programmable) | — |
| Cascadable | Yes (nCASC pin for multi-PROM chains) | — |
| JTAG Boundary Scan | Yes | — |
| Gehäuse | 8-pin PDIP (300-mil, through-hole) | PDIP-8 (Plastic DIP, 8-pin, 0.1" pitch) |
| Betriebstemperatur | -40 C to +85 C (industrial, suffix CEC) | — |
| Technology | CMOS EPROM cell | — |
| Compatible FPGA Families | FLEX 10K, APEX, ACEX, Cyclone, MAX (Altera / Intel FPGA) | ACEX 1K, APEX 20K, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, FLEX 8000, MAX 7000B/AE/S, MAX 9000, Mercury, Stratix, Stratix II, Arria |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | 1 (unlimited floor life) |
| Funktion | — | FPGA Configuration PROM |
| Maximum DCLK Frequency | — | 17.6 MHz (17.6 Mb/s effective bitstream rate) |
| Betriebstemperaturbereich | — | [DATA_NEEDED: full industrial range from datasheet] |
| Montageart | — | Through-Hole (DIP socketable) |
| Cascade Support | — | Not supported in DIP-8 package (nCASC pin not exposed) |
| Programming Interface | — | JTAG via Altera Quartus / Quartus Prime ByteBlaster |
| Error Detection | — | Built-in CRC during configuration transfer |
| Lead-Free / RoHS | — | Not lead-free (legacy Altera/Intel PC8 suffix is Sn-Pb finish); RoHS non-compliant variant |
| Pin-Anzahl | — | 8 |