EPC20LC20U vs EPC4QC100 Vergleich
Detaillierter Direktvergleich von EPC20LC20U von Intel und EPC4QC100 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC20LC20U | EPC4QC100 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,20 | $11,40 |
| Manufacturer | Altera Corporation (now Intel) | — |
| Funktion | FPGA Configuration Device (Serial Configuration PROM) | In-System Programmable Configuration PROM for FPGAs |
| Speichertyp | Non-volatile configuration memory | Flash |
| Configuration Interface | Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) | — |
| Operating Voltage | 5.0 V (typical) | — |
| Absolute Maximum DC Input | -0.3 V to 7.0 V | — |
| Transient Input Tolerance | -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) | — |
| Package Type | PLCC-20 (J-lead, plastic leaded chip carrier) | — |
| Pin-Anzahl | 20 | — |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount |
| Compatible FPGA Families | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone | Stratix, Cyclone, APEX, Mercury, ACEX |
| In-System Programming | Supported via JTAG / Quartus programmer | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Betriebstemperaturbereich | [DATA_NEEDED: industrial/commercial grade] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Lebenszyklusstatus | Obsolete / Last-time-buy in distribution | — |
| Speichergröße | — | 4 Mb |
| Supply Voltage (Core and I/O) | — | 3.3 V |
| Maximum Configuration Clock | — | 66 MHz |
| Schnittstelle | — | Serial / Fast Passive (Altera FPGAs) |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| JTAG Support | — | Yes (boundary scan + ISP via Jam STAPL) |
| nINIT_CONF Pin | — | Yes (triggers FPGA configuration via private JTAG instruction) |
| Gehäuse | — | 100-pin PQFP (20x14 mm) |
| Betriebstemperatur | — | 0C to +70C (commercial) |
| Lead-Free | — | unknown |