EPC2L20U vs EPC2LS20U Vergleich
Detaillierter Direktvergleich von EPC2L20U von Altera und EPC2LS20U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2L20U | EPC2LS20U |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,55 | $4,25 |
| Speichergröße | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Schnittstellentyp | Serial configuration (DCLK/DATA0) | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Supported FPGAs | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K | — |
| Configuration Mode | Single + Cascade (multi-PROM daisy chain) | — |
| Compression Support | Yes (FPGA decompresses bitstream) | — |
| Betriebstemperatur | -40C to +85C (industrial) | [DATA_NEEDED: Operating Temperature] |
| Gehäuse | 20-PLCC (PLCC-20) | 20-PLCC (J-lead, 9x9 mm) |
| Montageart | Surface Mount / Socket | — |
| JTAG Support | Yes (IEEE Std 1149.1 boundary scan) | Yes (IEEE 1149.1 boundary scan) |
| Pin-Anzahl | 20 | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL Level] |
| Product Type | — | In-System Programmable Configuration PROM |
| Memory Density | — | 1.6 Mbit |
| Operating Voltage (VCC) | — | 3.3 V |
| Schnittstelle | — | Altera serial configuration / JTAG |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | — | Yes (per "U" suffix) |
| Supported FPGA Families | — | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | — | PS (Passive Serial), AS, FPP |
| Done Pin | — | Yes (open-drain programmable polarity) |
| nSTATUS Pin | — | Yes (open-drain error flag) |
| nCONFIG Pin | — | Yes (reset/reconfiguration input) |
| DCLK Output | — | Yes (configuration clock to FPGA) |
| Compliance | — | RoHS (Pb-free per U suffix) |