EPC2LC20-U vs EPC2LC20N Vergleich
Detaillierter Direktvergleich von EPC2LC20-U von Altera und EPC2LC20N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LC20-U | EPC2LC20N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,60 | $7,40 |
| Speichertyp | Configuration PROM (Flash, in-system programmable) | Flash |
| Speichergröße | 1.6 Mbit | 1.6 Mbit |
| Schnittstelle | Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) | Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Max Configuration Clock | 10 MHz | — |
| Supply Voltage (VCC) | 3.3 V (3.0 V to 3.6 V) | — |
| Programmable | In-system via JTAG | — |
| Cascade Support | Yes (multi-PROM for larger bitstreams) | — |
| Gehäuse | 20-PLCC (9x9) | 20-pin PLCC (J-Lead, 9x9 mm) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: full operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K | Altera APEX, Cyclone, Stratix, ACEX, MAX 7000 |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | IEEE 1149.1 / IEEE 1532 compliant |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | — |
| Funktion | — | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage VCCIO | — | 4.75 V to 5.25 V |
| Configuration Clock Frequency | — | 8 MHz (max) |
| Packaging | — | Tube |