EPC2T32 vs EPC2TC32N Vergleich
Detaillierter Direktvergleich von EPC2T32 von Altera und EPC2TC32N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2T32 | EPC2TC32N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,70 | $9,20 |
| Product Type | FPGA Configuration PROM (non-volatile boot memory) | — |
| Speichergröße | 1.6 Mbit | 1.6 Mbit |
| Configuration Interface | Serial | — |
| Maximale Taktfrequenz | 10 MHz | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan + ISP) | — |
| Gehäuse | 32-pin TQFP (7x7 mm) | 32-TQFP (7x7 mm) |
| Versorgungsspannung | 3.3 V (5 V tolerant I/O per datasheet) | — |
| Betriebstemperatur | -40C to +85C (industrial) | 0 °C to +70 °C (Commercial) |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Cascadable | No (single-device configuration only) | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | — |
| Configuration Mode | Serial (DCLK/DATA/nCS) | Serial (AS) or Parallel (PS/AP) |
| Document Size (third-party) | 26 pages (per alldatasheet listing) | — |
| Manufacturer | — | Altera (now Intel) |
| Speichertyp | — | Flash Configuration PROM |
| Programmable Type | — | In System Programmable (ISP) |
| Schnittstelle | — | JTAG (IEEE 1149.1) + serial/parallel |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |