EPC2T32U vs EPC2-TC32 Vergleich
Detaillierter Direktvergleich von EPC2T32U von Altera und EPC2-TC32 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC2-TC32 - 1.6Mb ISP Configuration PROM | Altera | TQFP-32
EPC2-TC32 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC2T32U | EPC2-TC32 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,10 | $15,90 |
| Funktion | Configuration PROM for SRAM-based LUT FPGAs | — |
| Memory Density | 1.6 Mbit | — |
| Versorgungsspannung | 3.3 V or 5.0 V (user-selectable) | 3.3 V |
| Programmability | In-system programmable via JTAG (IEEE 1149.1) | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Configuration Modes Supported | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG | — |
| Gehäuse | 32-pin TQFP | 32-pin TQFP (7x7 mm) |
| Betriebstemperatur | Commercial / Industrial grade [DATA_NEEDED: exact range] | — |
| Cascading Support | Yes, via dedicated cascade port for density expansion | — |
| Compression Support | Altera bitstream decompression (up to 50% storage reduction) | — |
| Compatible FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K | — |
| Lead-Free Finish | Yes (per part suffix 'U') | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL rating] | MSL 3 (168 hours) |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| Hand-shake Pins | nSTATUS, nCONFIG, CONF_DONE | — |
| Speichertyp | — | EPROM (OTP/UV-erasable configuration PROM) |
| Speichergröße | — | 1.6 Mbit |
| Schnittstellentyp | — | Serial |
| Speicherorganisation | — | Serial bitstream output |
| Betriebstemperaturbereich | — | 0C to +70C (Commercial) |
| Supported FPGA Families | — | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Configuration Mode | — | Serial (FPP/MSD via FPGA master/slave) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |