EPC2TC32UCAD48 vs EPC2TC32N Vergleich
Detaillierter Direktvergleich von EPC2TC32UCAD48 von Altera und EPC2TC32N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2TC32UCAD48 | EPC2TC32N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,40 | $9,20 |
| Speichertyp | In-System Programmable Configuration PROM (Flash) | Flash Configuration PROM |
| Density | 1.6 Mbit | — |
| Configuration Clock | 10 MHz max | — |
| Schnittstelle | Serial (AS) / Parallel (FPP, PS) / JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) + serial/parallel |
| Versorgungsspannung | 3.3 V (typical) | — |
| Programmability | In-system via JTAG (ISP), 100,000 erase/write cycles | — |
| Betriebstemperaturbereich | -40 C to +85 C (industrial, U-suffix) | — |
| Gehäuse | 32-TQFP (7x7 mm, 0.8 mm pitch) | 32-TQFP (7x7 mm) |
| Pin-Anzahl | 32 | — |
| Cascade Support | Yes (multi-device daisy-chain) | — |
| Multi-Boot Support | Yes (Altera remote system upgrade) | — |
| Compatible FPGAs | Altera Cyclone, Stratix, APEX, ACEX, Mercury families | — |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | — |
| MSL-Level | 3 (168 hours) | — |
| Manufacturer | — | Altera (now Intel) |
| Speichergröße | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| Betriebstemperatur | — | 0 °C to +70 °C (Commercial) |
| Supported FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |
| Montageart | — | Surface Mount |
| Configuration Mode | — | Serial (AS) or Parallel (PS/AP) |