EPC2XXA vs EPC2LS20U Vergleich
Detaillierter Direktvergleich von EPC2XXA von Altera und EPC2LS20U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2XXA | EPC2LS20U |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,40 | $4,25 |
| Speichertyp | Configuration Flash (PROM) | — |
| Speichergröße | 1.6 Mbit | — |
| Configuration Interface | Passive Serial (PS) / Active Serial (AS) | — |
| Maximum Configuration Clock | 33 MHz | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan (ISP) | Yes (IEEE 1149.1 boundary scan) |
| Operating Voltage (VCC) | 3.0 V to 3.6 V | 3.3 V |
| Operating Voltage (VCCJ) | 1.8 V / 2.5 V / 3.3 V | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | [DATA_NEEDED: Operating Temperature] |
| Gehäuse | 20-pin SOIC (SO-20) 12.8 mm x 7.5 mm | 20-PLCC (J-lead, 9x9 mm) |
| Montageart | Surface Mount | — |
| Cascadable | Yes (daisy-chain multiple devices) | — |
| Programmer | Quartus II / Quartus Prime Programmer | — |
| Compatible FPGA Families | Cyclone, Cyclone II, Cyclone III, MAX II, MAX V, Stratix (selected) | — |
| RoHS-Status | Compliant | — |
| Lead-Free | Yes | — |
| Product Type | — | In-System Programmable Configuration PROM |
| Memory Density | — | 1.6 Mbit |
| Schnittstelle | — | Altera serial configuration / JTAG |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | — | Yes (per "U" suffix) |
| Supported FPGA Families | — | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | — | PS (Passive Serial), AS, FPP |
| Done Pin | — | Yes (open-drain programmable polarity) |
| nSTATUS Pin | — | Yes (open-drain error flag) |
| nCONFIG Pin | — | Yes (reset/reconfiguration input) |
| DCLK Output | — | Yes (configuration clock to FPGA) |
| MSL-Level | — | [DATA_NEEDED: MSL Level] |
| Compliance | — | RoHS (Pb-free per U suffix) |