EPC4QC100N vs EPC81500RC304-3 Vergleich
Detaillierter Direktvergleich von EPC4QC100N von Intel und EPC81500RC304-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC81500RC304-3 - Enhanced Configuration Device for SRAM FPGAs | Altera
EPC81500RC304-3 ObsoleteSpezifikationsvergleich
| Parameter | EPC4QC100N | EPC81500RC304-3 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,10 | $23,90 |
| Speichertyp | Flash (NOR, configuration PROM) | — |
| Speichergröße | 4 Mbit (4,194,304 bits) | — |
| Programmable Type | In System Programmable (ISP) | — |
| Configuration Interface | Serial / Parallel / JTAG (IEEE 1149.1) | — |
| Maximum DCLK Frequency | 66.7 MHz | — |
| On-Chip Decompression | Yes | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Typical Supply Voltage | 3.3 V | — |
| Betriebstemperatur | 0 C to 70 C (commercial) | — |
| Gehäuse | 100-pin PQFP (Plastic Quad Flat Pack) | 304-pin PQFP (RC304) |
| Package Dimensions | 20 x 14 mm | — |
| Pin Pitch | 0.65 mm | — |
| Montageart | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| Lead Free / RoHS | Yes (per chipdig datasheet excerpt) | — |
| Family | EPC4 Enhanced Configuration Device | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Device Type | — | Enhanced Configuration Device (Flash-based FPGA configuration memory) |
| Target FPGA Families | — | Altera FLEX 8000, FLEX 10K, ACEX 1K, APEX series SRAM-based LUT FPGAs |
| Configuration Memory Size | — | 8 Mbit |
| Interface Modes | — | Parallel-byte and serial bitstream modes |
| Programming Interface | — | JTAG (IEEE 1149.1) and byte-wide parallel |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage VCCIO | — | 3.3 V or 5.0 V tolerant |
| Betriebstemperaturbereich | — | 0 C to +70 C (commercial) |
| Pin-Anzahl | — | 304 |
| Configuration Clock | — | DCLK generated internally or externally to target FPGA |
| Multi-Device Support | — | Yes - daisy-chain configuration of multiple FPGAs |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |