EPC8Q1100 vs EPC8Q100 Vergleich
Detaillierter Direktvergleich von EPC8Q1100 von Altera und EPC8Q100 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC8Q1100 - 8 Mbit Enhanced Config Device for SRAM FPGAs | Altera
EPC8Q1100 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC8Q1100 | EPC8Q100 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $25,90 | $10,85 |
| Product Type | Enhanced Configuration Device (boot PROM) | — |
| Memory Density | 8 Mbit (8,388,608 bits) | 8 Mbit (8,388,608 bits) |
| Supported FPGAs | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur) | — |
| Configuration Interface | Altera Enhanced Config serial interface (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | Altera EPC serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, DONE) |
| Max DCLK Frequency | 33 MHz (Fast-mode) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Supply Voltage (VCCIO for FPGA interface) | 1.8 V / 2.5 V / 3.3 V tolerant | — |
| Programming Interface | IEEE Std 1149.1 JTAG (ISP) + serial byte-blaster mode | — |
| In-System Programmable | Yes | — |
| Gehäuse | 100-pin PQFP (plastic quad flat pack) | 100-pin PQFP (20 x 14 mm) |
| Betriebstemperatur | -40 C to +85 C (industrial) | — |
| Operating Current (active read) | [DATA_NEEDED: active ICC] | — |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Endurance (program/erase cycles) | [DATA_NEEDED: endurance cycles] | — |
| Data Retention | [DATA_NEEDED: data retention years] | [DATA_NEEDED: minimum years] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Speichertyp | — | NOR Flash, One-Time-Programmable (OTP) via JTAG |
| Supply Voltage VCC | — | 5.0 V (3.3 V core generated on-chip) |
| Internal Core Voltage | — | 3.3 V (on-chip LDO) |
| Maximum EPC Clock | — | 33 MHz |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| FPGA Compatibility | — | APEX 20K, APEX II, Cyclone, Cyclone II, Stratix, Stratix GX |
| Configuration Mode Support | — | FPP, PS, AS, JTAG (FPGA-dependent) |
| Program/Erase Endurance | — | [DATA_NEEDED: cycle count] |
| Betriebstemperaturbereich | — | 0 C to +70 C (commercial) |
| Storage Temperature Range | — | [DATA_NEEDED: range] |
| Montageart | — | Surface Mount |
| MSL-Level | — | [DATA_NEEDED: level] |
| Lead-Free / RoHS | — | [DATA_NEEDED: status] |