EPC8QC100T vs EPC8QC100DM Vergleich
Detaillierter Direktvergleich von EPC8QC100T von Intel und EPC8QC100DM von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC8QC100T | EPC8QC100DM |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | EEPROM |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,10 | $17,10 |
| Speichertyp | Flash configuration PROM | Non-volatile configuration PROM |
| Speichergröße | 8 Mbit | 8 Mb (1 MB) |
| Configuration Interface | Altera FPGA proprietary parallel | — |
| Programming Interface | IEEE 1149.1 (JTAG) in-system programmable | — |
| Data Compression | Yes (increases effective density) | — |
| Versorgungsspannung | 3.3 V | — |
| Supported FPGAs | Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K | — |
| Gehäuse | PQFP-100 (20x14 mm) | 100-PQFP (20 x 14 mm) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial / DM suffix) |
| Cascade Support | Yes (multi-device chains) | Yes - two EPC8 devices for 16 Mb |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | Compliant |
| MSL-Level | [DATA_NEEDED: MSL rating] | 1 (Unlimited) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Time | [DATA_NEEDED: typical configuration time] | — |
| Schnittstelle | — | Serial (Passive Serial / Passive Parallel Synchronous / Active Serial) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Maximum DCLK Frequency | — | 40 MHz |
| In-System Programming | — | Yes (IEEE 1149.1 / IEEE 1532 JTAG) |
| Lead-Free / Halogen-Free | — | Lead-free (per supplier); halogen status not in datasheet excerpt |
| Compatible FPGA Families | — | Cyclone, Cyclone II, Cyclone III, Stratix, Arria |
| Configuration Modes | — | PS, PPS, AS (with appropriate FPGA master) |
| Programming Cycles | — | [DATA_NEEDED: minimum erase/write endurance cycles] |