EPF10K100EQC208-1X vs EPF10K100EQC208-2 Vergleich

Detaillierter Direktvergleich von EPF10K100EQC208-1X von Intel und EPF10K100EQC208-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EPF10K100EQC208-1X EPF10K100EQC208-1X - 100K Gates FLEX 10KE FPGA, 208-PQFP | Intel

EPF10K100EQC208-1X - 100K Gates FLEX 10KE FPGA, 208-PQFP | Intel

EPF10K100EQC208-1X ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EPF10K100EQC208-1X EPF10K100EQC208-2
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $96,50 $155,85
Series FLEX 10KE FLEX 10KE
Family FLEX 10KE Field Programmable Gate Array —
Typical Gates 100,000 —
Logic Cells / Elements 4,992 —
Logic Array Blocks (LABs) 624 624
Embedded Memory Bits 49,152 —
Number of User I/Os 147 —
Number of DLLs 4 —
Maximum Operating Frequency 333.33 MHz —
Process Technology 0.22 µm CMOS SRAM —
Core Supply Voltage (VCCINT) 2.375 V to 2.625 V (2.5 V typical) —
I/O Supply Voltage (VCCIO) Multi-voltage 1.8 V / 2.5 V / 3.3 V / 5.0 V —
Gehäuse 208-BFQFP / 208-PQFP (28 x 28 mm) —
Speed Grade -1 (commercial, -1X extended temperature corner) -2
Montageart Surface Mount Surface Mount
RoHS-Status Compliant (per distributor listings) [DATA_NEEDED: not in provided source data]
Betriebstemperatur 0 °C to +70 °C commercial (extended grades available in family) 0 C to +70 C (Commercial)
Product Type — FPGA (Field Programmable Gate Array)
Typical Gate Count — 100,000 gates
Logic Elements (LEs) — 4,992
Total RAM Bits — 49,152 bits
Embedded Array Blocks (EABs) — 12 x 2,048 bits
Maximum User I/O — 147
Supply Voltage - Core (VCCINT) — 2.375 V to 2.625 V
Supply Voltage - I/O (VCCIO) — [DATA_NEEDED: VCCIO range, not in source data]
Gehäuse / Bauform — 208-BFQFP (PQFP, 28x28 mm)
Terminal Form — Gull Wing
Number of Terminals — 208
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
Configuration Method — Serial EEPROM / passive serial / JTAG

Datenblätter & Ressourcen

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