EPF10K100EQI208-2 vs EPF10K100EQC208-2 Vergleich
Detaillierter Direktvergleich von EPF10K100EQI208-2 von Intel und EPF10K100EQC208-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF10K100EQI208-2 | EPF10K100EQC208-2 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $155,85 |
| Family | FLEX 10KE | — |
| Logic Elements / Cells | 4,992 | — |
| Typical Gates | 100,000 | — |
| Embedded Memory (bits) | 49,152 | — |
| Logic Array Blocks (LABs) | 624 | 624 |
| User I/Os | 147 | — |
| Gehäuse | 208-pin PQFP (BFQFP) | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | — |
| Propagation Delay | 0.6 ns | — |
| Maximum Internal Frequency | 250 MHz | — |
| Betriebstemperatur | 0°C to 70°C (commercial) | 0 C to +70 C (Commercial) |
| Speed Grade | I (industrial temp), -2 timing | -2 |
| I/O Standards | 2.5 V / 3.3 V / 5 V tolerant | — |
| Configuration Interface | JTAG (IEEE 1149.1) / serial / parallel | — |
| Programming Method | In-system programmable (ISP) / SRAM-based | — |
| PCI Compliant | Yes | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: not in provided source data] |
| Series | — | FLEX 10KE |
| Product Type | — | FPGA (Field Programmable Gate Array) |
| Typical Gate Count | — | 100,000 gates |
| Logic Elements (LEs) | — | 4,992 |
| Total RAM Bits | — | 49,152 bits |
| Embedded Array Blocks (EABs) | — | 12 x 2,048 bits |
| Maximum User I/O | — | 147 |
| Supply Voltage - Core (VCCINT) | — | 2.375 V to 2.625 V |
| Supply Voltage - I/O (VCCIO) | — | [DATA_NEEDED: VCCIO range, not in source data] |
| Gehäuse / Bauform | — | 208-BFQFP (PQFP, 28x28 mm) |
| Montageart | — | Surface Mount |
| Terminal Form | — | Gull Wing |
| Number of Terminals | — | 208 |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Configuration Method | — | Serial EEPROM / passive serial / JTAG |