EPF10K130EBC356-1N vs EPF10K130EBC356-1 Vergleich
Detaillierter Direktvergleich von EPF10K130EBC356-1N von Altera und EPF10K130EBC356-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF10K130EBC356-1N | EPF10K130EBC356-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,20 | $95,00 |
| Family | FLEX 10KE | — |
| Typical Gates | 130,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates for EPF10K130E] | — |
| Logic Elements (LEs) | 6,656 | 6,656 |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count for EPF10K130E] | — |
| Total RAM Bits | 65,536 | — |
| User I/O Pins | 274 | — |
| Gehäuse | 356-LBGA | 356-LBGA (35x35 mm) |
| Package Code | LBGA | — |
| Logic Family | CMOS | CMOS |
| Process Technology | 0.22 µm | 0.22 µm SRAM |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V | — |
| Speed Grade | -1 | — |
| Propagation Delay | 0.6 ns | 0.6 ns |
| Maximum Internal Frequency | 333.33 MHz | — |
| Betriebstemperatur | 0 °C to 70 °C (Commercial) | 0C to +70C (Commercial) |
| JTAG Boundary-Scan | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V) | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N] | — |
| Series | — | FLEX 10KE |
| Device Family | — | FLEX-10KE Field Programmable Gate Array |
| Typical Gate Count | — | 130,000 gates |
| Embedded Memory (EABs) | — | 65,536 bits (8 Kbyte) / 12 EABs |
| Logic Array Blocks (LABs) | — | 832 |
| Maximum User I/O | — | 274 |
| Maximum Operating Frequency | — | 333 MHz |
| Core Voltage | — | 2.5 V |
| I/O Voltage | — | 3.3 V (5 V tolerant) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |