EPF10K30ATI144-2 vs EPF10K30ATC144-2N Vergleich
Detaillierter Direktvergleich von EPF10K30ATI144-2 von Altera und EPF10K30ATC144-2N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPF10K30ATC144-2N - FLEX-10KA 30K-Gate FPGA, 144-TQFP | Intel / Altera
EPF10K30ATC144-2N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPF10K30ATI144-2 | EPF10K30ATC144-2N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,95 | $33,40 |
| Series | FLEX 10KA | FLEX 10KA |
| Family | FLEX 10K Embedded Programmable Logic Family | — |
| Typical Gate Count | 30,000 gates | — |
| Logic Elements | 1,728 cells | 1728 |
| Embedded Array Blocks (EABs) | 12 | — |
| On-chip RAM | 12,288 bits | — |
| User I/O Pins | 246 (max for family), 102 in this 144-TQFP variant per DigiKey listing | — |
| Propagation Delay | 13 ns (per Microchip USA) | 0.6 ns (per datasheet propagation path) |
| Speed Grade | -2 | — |
| Process Technology | 0.42 µm CMOS, 4 metal layers | 0.3 µm CMOS, SRAM-based |
| Core Voltage | 5.0 V | — |
| I/O Voltage Compatibility | 5.0 V / 3.3 V / 2.5 V | — |
| Gehäuse | 144-pin TQFP (TQFP-144), 0.500 mm pitch | — |
| Betriebstemperatur | -40 °C to +85 °C (industrial, 'I' suffix) | 0 °C to 70 °C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| Configuration Method | SRAM, in-system programmable | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS-Status | Unknown (legacy Altera product line; verify with supplier) | — |
| Typical Gates | — | 30,000 |
| Total RAM Bits | — | 12288 |
| Number of LABs/CLBs | — | 216 |
| Number of I/O | — | 102 |
| Voltage Supply | — | 3.0 V to 3.6 V |
| Gehäuse / Bauform | — | 144-LQFP / 144-TQFP |
| Internal Frequency (max) | — | 142.86 MHz |
| Programming Interface | — | JTAG (IEEE 1149.1) via ByteBlaster / USB-Blaster |
| Lead-Free / Finish | — | Yes (NiPdAu lead finish) |