EPF10K50VQC240-2 vs EPF10K50VRC240-1 Vergleich
Detaillierter Direktvergleich von EPF10K50VQC240-2 von Altera und EPF10K50VRC240-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF10K50VQC240-2 | EPF10K50VRC240-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $28,75 | $130,32 |
| Family | FLEX 10K | FLEX 10K |
| Series | FLEX-10K | — |
| Typical Gate Count | 50,000 gates | — |
| Logic Elements (LABs) | 360 | — |
| Logic Cells | 2,880 | — |
| Embedded Array Memory | 20,480 bits | — |
| User I/O Pins | 189 | — |
| Gehäuse | 240-BFQFP (240-PQFP / FQFP / QFP-240) | 240-RQFP Exposed Pad |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Package Code | FQFP | — |
| Package Shape | Square | — |
| Process Technology | 0.42 micrometer CMOS, 4-layer metal | 0.42 µm CMOS |
| Core Supply Voltage | 3.3 V | — |
| I/O Supply Voltage (MultiVolt) | 5.0 V / 3.3 V / 2.5 V | — |
| Maximum Internal Frequency | 125 MHz | — |
| Propagation Delay (typical) | 0.6 ns | — |
| Betriebstemperatur | 0 C to +70 C (Commercial) | 0 °C to +70 °C (Commercial) |
| Temperature Grade | Commercial | — |
| Configuration Scheme | SRAM-based, serial / parallel via EPC1/EPC2 | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status - legacy Altera FLEX 10K family typically non-RoHS Pb-bearing BFQFP; verify on distributor listing] | Compliant |
| Logic Elements | — | 2,880 |
| Typical Gates | — | 50,000 |
| Embedded Memory | — | 20,480 bits (189 Kb) |
| User I/O | — | 274 (max) |
| Number of I/O Pins | — | 189 |
| Pins | — | 240 |
| Core Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) |
| Internal Frequency (max) | — | 66.67 MHz |
| Propagation Delay | — | 0.6 ns |
| Logic Family | — | CMOS |
| JTAG Support | — | Yes (IEEE Std 1149.1-1990) |
| Configuration Interface | — | JTAG / BitBlaster / ByteBlasterMV / Jam STAPL |
| Programming Language | — | Altera MAX+PLUS II / Quartus |