EPF6010ANTC100-1 vs EPF6010ANTC100-2 Vergleich
Detaillierter Direktvergleich von EPF6010ANTC100-1 von Intel und EPF6010ANTC100-2 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPF6010ANTC100-2 - FLEX 6000 FPGA, 880 LEs, 71 I/O, 100-TQFP | Intel
EPF6010ANTC100-2 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPF6010ANTC100-1 | EPF6010ANTC100-2 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,50 | $17,50 |
| Series | FLEX 6000 | — |
| Manufacturer | Intel (formerly Altera) | — |
| Number of LABs/CLBs | 88 | — |
| Number of Logic Elements/Cells | 880 | — |
| Total RAM Bits | 0 (no embedded block RAM) | — |
| Number of I/O | 71 | — |
| Number of Gates | 10000 | — |
| Voltage - Supply | 3.0 V to 3.6 V | — |
| Montageart | Surface Mount | Surface Mount |
| Gehäuse | 100-pin TQFP | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| Betriebstemperatur | [DATA_NEEDED: full industrial/commercial range] | Commercial (0C to +70C) |
| Configuration Memory | SRAM (volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1), serial passive | IEEE 1149.1 (JTAG) / passive serial / EPC configuration device |
| Process Technology | [DATA_NEEDED: process node] | — |
| Part Status | Obsolete | — |
| RoHS-Status | [DATA_NEEDED: confirmed from datasheet] | [DATA_NEEDED: RoHS compliance] |
| Family | — | FLEX 6000 / FLEX 6000A |
| Logic Elements | — | 880 |
| Programmable I/O Pins | — | 71 |
| Speed Grade | — | -2 |
| Configuration Method | — | SRAM (volatile), in-system programmable |
| Supply Voltage (VCCINT) | — | 5.0 V (FLEX 6000A); 3.3 V (FLEX 6000) |
| I/O Standards Supported | — | TTL, CMOS, PCI (with clamping diodes) |
| Number of LABs | — | [DATA_NEEDED: LAB count] |
| Embedded Memory | — | [DATA_NEEDED: embedded RAM blocks] |
| Global Clock Networks | — | [DATA_NEEDED: global clock count] |
| MSL-Level | — | 3 (168 hours) |
| Packaging | — | Tray (per Altera packing standard) |