EPF6016ATI144-3N vs EPF6016TC144-3U Vergleich
Detaillierter Direktvergleich von EPF6016ATI144-3N von Altera und EPF6016TC144-3U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPF6016ATI144-3N - FLEX 6000 FPGA 16K Gates 117 I/O | Altera / Intel
EPF6016ATI144-3N ⚠ Letzte BestellmöglichkeitAltera
EPF6016TC144-3U - FLEX 6000 FPGA 16K Gates 1320 Cells TQFP-144 | Altera
EPF6016TC144-3U ObsoleteSpezifikationsvergleich
| Parameter | EPF6016ATI144-3N | EPF6016TC144-3U |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,10 | $19,80 |
| Family | FLEX 6000 | FLEX 6000 |
| Logic Elements | 1,320 | — |
| Logic Array Blocks (LABs) | 132 | — |
| Equivalent Gates | 16,000 | — |
| User I/O | 117 | — |
| Dedicated Inputs | 4 | — |
| Gehäuse | 144-pin TQFP (LQFP-144) | TQFP-144 (TC144), 0.5 mm pitch |
| Process Technology | 0.42 µm CMOS, SRAM | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Internal Frequency | 142.86 MHz max | 172 MHz (max) |
| Betriebstemperatur | -40 °C to +85 °C (industrial) | [DATA_NEEDED: industrial range from 'U' suffix] |
| Speed Grade | -3 | -3 |
| Montageart | Surface Mount | Surface Mount |
| Configuration | SRAM, in-system programmable via JTAG | — |
| Lead-Free / RoHS | Yes (N suffix) | — |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| Series | — | EPF6016 |
| Device Type | — | FPGA - Field Programmable Gate Array |
| Logic Elements (LEs) | — | 1320 |
| Total Logic Cells | — | 1320 |
| Typical Gates | — | 16000 |
| Maximum Gates | — | 24000 |
| User I/Os | — | 117 |
| Pin-Anzahl | — | 144 |
| Pin-to-Pin Logic Delay | — | 4 ns (speed grade -3) |
| Versorgungsspannung | — | [DATA_NEEDED: VCCINT and VCCIO values] |
| RoHS-Status | — | Compliant (verified by 'U' suffix marking convention) |
| Configuration Method | — | SRAM-based, EPC1/EPC2 PROM or JTAG (IEEE 1149.1) |