EPF81188AGC232-4N vs EPF81188AGC232-2A Vergleich
Detaillierter Direktvergleich von EPF81188AGC232-4N von Altera und EPF81188AGC232-2A von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPF81188AGC232-4N - 12K-Gate FLEX 8000 FPGA, 5V, CPGA-232 | Altera
EPF81188AGC232-4N ObsoleteSpezifikationsvergleich
| Parameter | EPF81188AGC232-4N | EPF81188AGC232-2A |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $82,00 | $92,00 |
| Family | FLEX 8000 | FLEX 8000 |
| Logic Elements / Cells | 1,008 cells | — |
| Usable Gates | 12,000 | 12,000 |
| Maximum Registers | 1,500 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Propagation Delay | 5.5 ns (speed grade -4) | 5 ns |
| Process Technology | 0.42 µm CMOS | 0.42 µm CMOS |
| Supply Voltage (VCCINT) | 5 V | — |
| Gehäuse | 232-pin CPGA (Ceramic Pin Grid Array) | CPGA-232 (Ceramic Pin Grid Array, 232 pins) |
| Configuration Method | Serial (EPC1/EPC2) or JTAG (IEEE 1149.1) | — |
| In-Circuit Reconfigurable | Yes (ICR) | — |
| Operating Temperature Grade | Industrial / Military (per -N suffix) | — |
| Montageart | Through-hole (CPGA socket or solder) | Through-Hole (CPGA) |
| RoHS-Status | Compliant (lead-free per distributor listing) | [DATA_NEEDED: RoHS compliance status] |
| Programming Interface | JTAG / Altera ByteBlaster compatible | — |
| Logic Elements | — | 1,008 |
| Logic Cells | — | 1,008 |
| Maximum Internal Frequency | — | 125 MHz |
| User I/O Pins | — | 184 |
| Dedicated Inputs | — | 4 |
| Configuration Technology | — | SRAM (volatile, in-system reconfigurable) |
| I/O Voltage | — | 3.3 V or 5 V (configurable) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature grade] |
| In-Circuit Reconfigurability | — | Yes (external configuration device or intelligent host) |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Output Function | — | Registered (D-type flip-flop per LE) |