EPF81188AQC240-3 vs EPF10K50VQC240-2 Vergleich
Detaillierter Direktvergleich von EPF81188AQC240-3 von Altera und EPF10K50VQC240-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF81188AQC240-3 | EPF10K50VQC240-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $30,00 | $28,75 |
| Manufacturer | Altera (now Intel) | — |
| Series | FLEX 8000 | FLEX-10K |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Usable Gates | 12,000 | — |
| Logic Cells / Elements | 1,008 | — |
| Logic Array Blocks (LABs) | 126 | — |
| User I/Os | 184 | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Process Technology | 0.42 µm CMOS | 0.42 micrometer CMOS, 4-layer metal |
| Versorgungsspannung | 4.75 V to 5.25 V (5 V nominal) | — |
| Speed Grade | -3 | — |
| Betriebstemperatur | 0 °C to +70 °C (Commercial) | 0 C to +70 C (Commercial) |
| Gehäuse | 240-pin PQFP (BFQFP) 32x32 mm | 240-BFQFP (240-PQFP / FQFP / QFP-240) |
| Configuration Method | SRAM, loaded at power-up via EPC1/EPC1213/EPC1064/EPC1441 or controller | — |
| Boundary-Scan Support | JTAG IEEE 1149.1 | — |
| RoHS-Status | Non-compliant (per ICComponents listing) | [DATA_NEEDED: RoHS status - legacy Altera FLEX 10K family typically non-RoHS Pb-bearing BFQFP; verify on distributor listing] |
| In-Circuit Reconfigurability | Yes (ICR) | — |
| Family | — | FLEX 10K |
| Typical Gate Count | — | 50,000 gates |
| Logic Elements (LABs) | — | 360 |
| Logic Cells | — | 2,880 |
| Embedded Array Memory | — | 20,480 bits |
| User I/O Pins | — | 189 |
| Number of Terminals | — | 240 |
| Terminal Form | — | Gull Wing |
| Package Code | — | FQFP |
| Package Shape | — | Square |
| Core Supply Voltage | — | 3.3 V |
| I/O Supply Voltage (MultiVolt) | — | 5.0 V / 3.3 V / 2.5 V |
| Maximum Internal Frequency | — | 125 MHz |
| Propagation Delay (typical) | — | 0.6 ns |
| Temperature Grade | — | Commercial |
| Configuration Scheme | — | SRAM-based, serial / parallel via EPC1/EPC2 |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Montageart | — | Surface Mount |