EPF8820AQC208-2N vs EPF8820ARI208-2N Vergleich
Detaillierter Direktvergleich von EPF8820AQC208-2N von Altera und EPF8820ARI208-2N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF8820AQC208-2N | EPF8820ARI208-2N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,10 | $99,50 |
| Family | FLEX 8000 | FLEX 8000 |
| Logic Elements | 672 | 504 |
| Usable Gates | 8,000 | 8,820 |
| User I/O Pins | 152 | — |
| Dedicated Inputs | 4 | — |
| Process Technology | 0.42 µm CMOS | — |
| Versorgungsspannung | 5 V | — |
| I/O Standard Support | 3.3 V / 5 V (multiVolt) | — |
| Maximum Frequency | 125 MHz | — |
| Propagation Delay | 5 ns | — |
| Gehäuse | 208-pin PQFP (FQFP) | 208-pin RQFP (Plastic Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 °C to +70 °C (Commercial) | 0C to +70C (commercial) / -40C to +85C (industrial) |
| Configuration Method | SRAM (external EPROM/EPC device) | Passive serial / JTAG / Altera EPC configuration device |
| Logic Family | CMOS | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance per specific date code] |
| Maximum User I/O | — | 78 |
| LABs (Logic Array Blocks) | — | 63 |
| Logic Elements per LAB | — | 8 |
| Speed Grade | — | -2 (mid-tier) |
| Core Supply Voltage | — | 5.0 V |
| Programming Technology | — | SRAM (volatile, requires configuration device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Lead-Free | — | Yes (N suffix indicates lead-free assembly) |