EPF8820ARC240-3 vs EPF8820ARC240-4 Vergleich
Detaillierter Direktvergleich von EPF8820ARC240-3 von Altera und EPF8820ARC240-4 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPF8820ARC240-3 - FLEX 8000 FPGA 672 LE | Intel/Altera | 240-pin RQFP
EPF8820ARC240-3 ObsoleteSpezifikationsvergleich
| Parameter | EPF8820ARC240-3 | EPF8820ARC240-4 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $24,00 | $17,20 |
| Family | FLEX 8000 | FLEX 8000 |
| Device Model | EPF8820 | — |
| Logic Elements | 672 | 672 |
| Usable Gates | ~8,000 | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: number of EABs] | 16 |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| Process Technology | 0.42 µm CMOS, 3-layer metal | CMOS SRAM |
| Configuration Memory | SRAM-based (volatile), ISP via JTAG | — |
| Speed Grade | -3 | -4 |
| Gehäuse | RQFP-240 (240-pin) | RQFP-240 (240-pin Reduced Quad Flat Pack) |
| Pin/Package Designator | RC240 | — |
| Montageart | Surface Mount | Surface Mount (RQFP) |
| Core Supply Voltage | 5.0 V ±5% (4.75V to 5.25V) | — |
| I/O Standards | 5.0V PCI, 3.3V LVTTL/LVCMOS | — |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Interface | JTAG (IEEE 1149.1), passive serial/parallel, EPC | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Typical Gates | — | 8000 usable gates |
| Maximum RAM Bits | — | 4096 bits |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5.0 V |
| Programmability | — | SRAM, in-system via JTAG (IEEE 1149.1) |
| Configuration Schemes | — | Passive serial, passive parallel, JTAG |