EPF8820ARI208-1 vs EPF8820ARC208-3 Vergleich
Detaillierter Direktvergleich von EPF8820ARI208-1 von Altera und EPF8820ARC208-3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoleteSpezifikationsvergleich
| Parameter | EPF8820ARI208-1 | EPF8820ARC208-3 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $20,40 | $62,00 |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Technology | SRAM-based, 0.42 µm CMOS | — |
| Usable Gates | 8,000 | 8,000 |
| Logic Elements (LEs) | 672 | — |
| Flip-Flops | 820 | — |
| Maximum User I/O | 152 | — |
| Embedded Memory | [DATA_NEEDED: embedded memory bits] | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Standards | 3.3 V or 5 V configurable | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Gehäuse | 208-pin RQFP | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40 °C to +85 °C (industrial) | — |
| Configuration Interface | JTAG / IEEE 1149.1 + serial/parallel EPROM | — |
| Process Geometry | 0.42 µm | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 8000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | 0.42 µm CMOS |
| Configuration Memory | — | SRAM (volatile) |
| Gehäuse / Bauform | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |