EPM1270T144C5N vs EPM3128ATC144-7 Vergleich
Detaillierter Direktvergleich von EPM1270T144C5N von Altera und EPM3128ATC144-7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM1270T144C5N - MAX II CPLD, 980 LEs, 212 I/O, TQFP-144 | Intel/Altera
EPM1270T144C5N ✓ AktivSpezifikationsvergleich
| Parameter | EPM1270T144C5N | EPM3128ATC144-7 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,75 | $8,10 |
| Family | MAX II | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 980 | — |
| Logic Elements (LEs) | 1270 | — |
| Maximum User I/Os | 212 | — |
| Number of Logic Array Blocks (LABs) | 127 | — |
| Process Technology | 0.18 µm | CMOS EEPROM |
| Propagation Delay (tPD) | 6.2 ns | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Supply Voltage (Core) | 2.5 V / 3.3 V | — |
| Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Gehäuse | TQFP-144 (T144), 22 x 22 mm, 0.5 mm pitch | TQFP-144 (22x22 mm) |
| Betriebstemperatur | 0 °C to +85 °C (Commercial) | 0C to +70C (Commercial) |
| Speed Grade | -5 | -7 |
| Programming Interface | JTAG (IEEE 1149.1), In-System Programmable | — |
| Configuration Memory | Internal flash (non-volatile, instant-on) | — |
| RoHS-Status | Compliant (lead-free) | — |
| Halogenfrei | Compliant | — |
| Montageart | Surface Mount | Surface Mount |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| User I/Os | — | 96 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Pin-to-Pin Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency (fCNT) | — | 129.9 MHz |
| Programming Technology | — | CMOS EEPROM (in-system programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan + ISP |