EPM3032ALC44-10N vs EPM3032ALC44-7N Vergleich
Detaillierter Direktvergleich von EPM3032ALC44-10N von Altera und EPM3032ALC44-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3032ALC44-10N | EPM3032ALC44-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,94 | $1,05 |
| Family | MAX 3000A | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 600 gates | 600 usable gates |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 2 | — |
| User I/O Pins | 34 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal fMAX | 103.1 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Yes, IEEE 1149.1 compliant | — |
| Gehäuse | 44-pin PLCC (J-Lead, surface mount) | 44-PLCC (J-Lead, 16.59 x 16.59 mm) |
| Montageart | Surface Mount | Surface Mount (PLCC socket compatible) |
| Betriebstemperatur | [DATA_NEEDED: industrial/commercial range] | 0C to +70C (commercial grade) |
| RoHS-Status | [DATA_NEEDED: compliant or non-compliant] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Altera (Intel) |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 32 |
| Propagation Delay (tPD1) | — | 7.5 ns (max, pin-to-pin) |
| Internal Counter Frequency (fCNT) | — | 227.3 MHz (max) |
| Number of Logic Elements / Blocks | — | 2 LABs (16 macrocells each) |
| Number of I/O Pins | — | 34 usable I/O (44 total package pins) |
| Number of Dedicated Inputs | — | 4 |
| Programmable Type | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Speichertyp | — | EEPROM (non-volatile, 100 program/erase cycles) |
| Supply Voltage - Internal (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Bank Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| MSL-Level | — | 3 (168 hours) |
| Process Technology | — | CMOS EEPROM |