EPM3032ALC44-4 vs EPM3032ALC44-4N Vergleich
Detaillierter Direktvergleich von EPM3032ALC44-4 von Altera und EPM3032ALC44-4N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3032ALC44-4 | EPM3032ALC44-4N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1,10 | $1,32 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | 34 |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 4.5 ns |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Usable Gates | 600 to 10,000 (MAX 3000A family range) | 600 |
| Gehäuse | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-Lead) |
| Betriebstemperatur | 0°C to +70°C (Commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability (ISP) | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Programming Interface | JTAG (ByteBlaster / MasterBlaster) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: from datasheet] |
| Montageart | Surface Mount (PLCC J-Lead) | Surface Mount |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum Counter Frequency (fCNT) | — | 227.3 MHz |
| Programmability | — | EEPROM (non-volatile), IEEE 1149.1 JTAG ISP, IEEE 1532 compliant |