EPM3032ALC44-7N vs EPM3064ALC44-7N Vergleich
Detaillierter Direktvergleich von EPM3032ALC44-7N von Altera und EPM3064ALC44-7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3032ALC44-7N | EPM3064ALC44-7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1,05 | $3,95 |
| Manufacturer | Altera (Intel) | — |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 32 | — |
| Logic Gates | 600 usable gates | — |
| Propagation Delay (tPD1) | 7.5 ns (max, pin-to-pin) | — |
| Internal Counter Frequency (fCNT) | 227.3 MHz (max) | — |
| Number of Logic Elements / Blocks | 2 LABs (16 macrocells each) | — |
| Number of I/O Pins | 34 usable I/O (44 total package pins) | — |
| Number of Dedicated Inputs | 4 | — |
| Programmable Type | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | — |
| Speichertyp | EEPROM (non-volatile, 100 program/erase cycles) | — |
| Supply Voltage - Internal (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Bank Voltage (VCCIO) | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Betriebstemperatur | 0C to +70C (commercial grade) | 0C to +70C (commercial) |
| Gehäuse | 44-PLCC (J-Lead, 16.59 x 16.59 mm) | 44-pin PLCC |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | CMOS EEPROM | — |
| Family | — | MAX 3000A |
| Logic IC Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 2 |
| Usable Gates | — | 1,250 |
| Number of User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Frequency | — | 135.1 MHz |
| Core Technology | — | CMOS EEPROM |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Tolerance | — | 5 V-tolerant |
| In-System Programmability | — | Yes (IEEE Std 1149.1 JTAG) |
| Programming Software | — | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) |