EPM3032ATC44-10NAB vs EPM3032ATC44-10NAA Vergleich
Detaillierter Direktvergleich von EPM3032ATC44-10NAB von Intel und EPM3032ATC44-10NAA von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3032ATC44-10NAB - 32-Macrocell CPLD, 10ns, 3.3V | Intel (Altera)
EPM3032ATC44-10NAB ObsoleteAltera
EPM3032ATC44-10NAA - 32-Macrocell MAX 3000A CPLD, 44-TQFP | Altera
EPM3032ATC44-10NAA ObsoleteSpezifikationsvergleich
| Parameter | EPM3032ATC44-10NAB | EPM3032ATC44-10NAA |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,10 | $9,95 |
| Product Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Logic Elements / Macrocells | 32 macrocells | — |
| Usable Gates | 600 | 600 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 103.1 MHz (per Arrow listing) | — |
| Number of User I/O | 34 (max for 44-pin TQFP package) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt I/O compatible with 5.0 V, 3.3 V, 2.5 V logic) | — |
| Gehäuse | 44-pin TQFP | 44-pin TQFP |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE Std. 1149.1 / IEEE Std. 1532 ISP) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Hot-Socketing Support | Yes | Yes |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | Compliant (per -NAB suffix convention) | [DATA_NEEDED: RoHS status] |
| Delivery Form | Tray ('AB' suffix per Altera order code convention) | — |
| Process Technology | CMOS, EEPROM-based | — |
| Family | — | MAX 3000A |
| Number of Macrocells | — | 32 |
| Number of Logic Array Blocks (LABs) | — | 2 |
| Number of User I/O Pins | — | 34 |
| Propagation Delay (tpd) | — | 10 ns |
| Maximum Internal Frequency | — | [DATA_NEEDED: fmax spec] |
| Core Supply Voltage | — | 3.3 V |
| I/O Logic Levels Supported | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1149.1 JTAG + IEEE Std. 1532 |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |