EPM3064ALC44-10N vs EPM3064ATC44-10NAF Vergleich
Detaillierter Direktvergleich von EPM3064ALC44-10N von Altera und EPM3064ATC44-10NAF von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteAltera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndSpezifikationsvergleich
| Parameter | EPM3064ALC44-10N | EPM3064ATC44-10NAF |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,25 | $5,05 |
| Product Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 34 | — |
| Usable Gates | 1,250 | 1250 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | 3.0 V to 3.6 V (MultiVolt) | — |
| Configuration Memory | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) | — |
| Gehäuse | 44-pin PLCC (LC44) | TQFP-44 (10x10 mm) |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: commercial / industrial grade] | [DATA_NEEDED: industrial/commercial grade] |
| RoHS-Status | Compliant | Compliant |
| Open-Drain Output Option | Yes (per I/O pin) | — |
| Output Slew-Rate Control | Programmable | — |
| Series | — | MAX 3000A |
| Macro Cells | — | 64 |
| Logic Elements / LABs | — | 4 LABs (16 macrocells per LAB) |
| Number of I/O Pins | — | 34 |
| Propagation Delay (tPD, max) | — | 10 ns |
| I/O Voltage Tolerance | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) |
| Programmable Technology | — | EEPROM (non-volatile) |
| In-System Programmable | — | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | — | Yes (IEEE Std. 1149.1 JTAG) |
| Pin-Locking | — | Yes |
| Lead Finish | — | Lead-free (NiPdAu, AF suffix) |
| Configuration Memory Cycles | — | 100 erase/program cycles |